1. Field of the Invention
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a high-voltage power semiconductor device.
2. Description of the Related Art
Background Art
FIG. 49 is a top view of a conventional horizontal n-channel IGBT (Insulated Gate Bipolar Transistor) generally denoted at 700. FIG. 50 is a cross sectional view of FIG. 49 taken along the direction X-X.
As shown in FIG. 50, the IGBT 700 includes a p-type substrate 1. The p-type substrate 1 seats an n− layer 2 in which an n-type buffer layer 3 is formed. There is a p-type collector layer 4 in the n-type buffer layer 3.
A p-type base layer 5 is formed in the n− layer 2, over a predetermined distance from the p-type collector layer 4. In the p-type base layer 5, an n-type emitter layer (n+) 6 is formed so that it is on the inner side relative to a peripheral portion of the p-type base layer 5 and shallower than the p-type base layer 5. A p-type emitter layer (p+) 7 as well is formed in the p-type base layer 5.
A field oxide film 8 is formed on the surface of the n− layer 2 which is located between the n-type buffer layer 3 and the p-type base layer 5. On a channel region 15 formed in the p-type base layer 5 and located between the emitter layer 6 and the n− layer 2, a gate wire 10 is disposed via a gate oxide film 9. Further, there is a protection film 11 which is disposed covering the field oxide film 8 and the like.
A gate electrode 12 is disposed such that it is electrically connected with the gate wire 10. An emitter electrode 13 is further disposed such that it is electrically connected with both the n-type emitter layer 6 and the p-type emitter layer 7. In addition, a collector electrode 14 is disposed such that it is electrically connected with the p-type collector layer 4. The emitter electrode 13, the collector electrode 14 and the gate electrode 12 are electrically isolated from each other.
As shown in FIG. 49, the p-type collector layer 4 is located at the center of the IGBT 700 in which structure the n-type buffer layer 3, the n− layer 2, the p-type base layer 5, the n-type emitter layer 6 and the p-type emitter layer 7 surround the p-type collector layer 4 in this order, and this structure has an endless shape which is defined by connecting two semi-circular sections by straight sections. For easy understanding, FIG. 49 omits the field oxide film 8, the gate oxide film 9, the gate wire 10, the gate electrode 12, the protection film 11, the emitter electrode 13 and the collector electrode 14 (JPB 3647802).